Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.

In this hybrid role, you will be reporting to the Head of Compute.

You will:

• Structure and drive custom silicon partnerships
• Audit and collaborate with partners to optimize their PD flows and methodologies
• Work closely with internal, program management, and external teams to ensure PD implementation meets design performance and schedule goals, including adjacent areas such as DFT, power, and reliability
• Review all final PD, timing, electrical, etc. sign-off for tape-out approval
• Escalate program risks or resource gaps
• Manage a small internal team of PD experts

You have:

• Strong team management, leadership, and communication skills,  with experience coordinating  internal and external activities
• 5+ years of experience leading physical design of high performance SoCs or ASICs
• Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, P&R, clocking, timing closure, floor plan, power and IO planning
• Experience in designing digital logic and/or Design For Testability (DFT) structures in System Verilog or equivalent

We prefer:

• Track record of successfully driving custom / semi-custom silicon engagements with external partners
• Experience with automotive silicon quality, reliability, and safety requirements and processes
• Mixed signal design and characterization
• Experience drafting and negotiating technical portions of contracts and SoWs
• Familiar with chiplet or multi-chip packaging